A memory management unit (MMU) is a component responsible for handling accesses to memory requested by the central processing unit (CPU) in a data processing system. The MMU is usually resident in the random access memory (RAM) portion of the data processing system. The CPU provides the MMU with a virtual memory address when requesting data from the memory. The MMU is responsible for translating the virtual memory address into a physical memory address corresponding to the actual physical memory location. To do this, the MMU usually consults a cached translation lookaside buffer (TLB). The TLB is a subset of a complete page address table and may change over time. The complete address table usually resides in the main memory. Because the TLB may change over time, a cache coherence problem may arise in multi-processor systems with multiple MMUs since each MMU may have its own TLB and the TLBs may not comprise the same entries. Furthermore, because the TLB comprises only a subset of the complete page address table, some memory requests from the CPU may result in a cache miss. In such cases, the MMU must then consult the complete page address table which increases latency.
Additionally, the MMU may be responsible for page protection of the data in the RAM to prevent or deny access to the data if the privilege level of the request from the CPU is not sufficiently high. This prevents unauthorized reading and/or modification of the data in the RAM. The page translation table, in addition to containing entries translating virtual addresses to physical addresses, may also contain a privilege levels that may be associated with each virtual address. The TLB may contain a subset of virtual address and privilege level correlations. The MMU may check the TLB to determine the privilege required to access the data associated with the virtual address. However, the since the TLB does not include the entire page translation table, there is a chance that the MMU will not be able to determine whether the data request is authorized without additionally consulting the complete translation table. If this is necessary, the time to determine whether the data request is authorized may be increased. Furthermore, as with address translation, the cache coherence problem of the TLB may also compromise the ability of the MMU to perform its page protection mechanisms.